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ASAHI KASEI
[AK93C85A/95A/10A]
AK93C85A / 95A / 10A
16K / 32K / 64Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.8V to 5.5V AK93C85A 16384 bits, 1024 x 16 organization AK93C95A 32768 bits, 2048 x 16 organization AK93C10A 65536 bits, 4096 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 0.4mA Max. Read Operation - 0.8A Max. Standby High Reliability - Endurance : 100K cycles - Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE (Max. 8ms: VCC=4.5V to 5.5V) Busy/Ready status signal Software controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (SOP, SSOP)
DO
DATA REGISTER
16 16
DI
INSTRUCTION REGISTER
R/W AMPS AND AUTO ERASE
INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION
EEPROM
93C85A=16384bit 93C95A=32768bit 93C10A=65536bit
ADD. BUFFERS
DECODER
CS
VPP SW
SK
VREF
VPP GENERATOR
Block Diagram
DAM02E-03 -12004/05
ASAHI KASEI
[AK93C85A/95A/10A]
General Description
The AK93C85A/95A/10A is a 16384/32768/65536-bit serial CMOS EEPROM divided into 1024/2048/4096 registers of 16 bits each. The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C85A/95A/10A. The AK93C85A/95A/10A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C85A/95A/10A, consisting of chip select (CS), serial clock (SK), data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C85A/95A/10A takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C85A/95A/10A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output.
Software controlled write protection When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (tCS). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
Type of Products Model AK93C85AM AK93C95AF AK93C10AF Memory size 16K bits 32K bits 64K bits Temp. Range -40C to +85C -40C to +85C -40C to +85C VCC 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V Package 8pin Plastic SSOP 8pin Plastic SOP 8pin Plastic SOP
DAM02E-03 -2-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
Pin Arrangement
AK93C85AM
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC NC GND
8pin SSOP
AK93C95AF/10AF
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC NC GND
8pin SOP
Pin Name CS SK DI DO GND VCC NC
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Not Connected *1
*1: Please Open NC pin.
DAM02E-03 -3-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
Functional Description
The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of 250ns (tCS) between each instruction when the instruction is continuously executed. Instructi Start Op on Bit Code READ 01 10 WRITE 01 01 EWEN 01 00 EWDS 01 00 WRAL 01 00 Address A9-A0 A9-A0 11XXXXXXXX 00XXXXXXXX 01XXXXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table1. Instruction Set for the AK93C85A Instructi Start Op on Bit Code READ 1 10 WRITE 1 01 EWEN 1 00 EWDS 1 00 WRAL 1 00 Address A10-A0 A10-A0 11XXXXXXXXX 00XXXXXXXXX 01XXXXXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table2. Instruction Set for the AK93C95A Instructi Start Op Address on Bit Code READ 1 10 A11-A0 WRITE 1 01 A11-A0 EWEN 1 00 11XXXXXXXXXX EWDS 1 00 00XXXXXXXXXX WRAL 1 00 01XXXXXXXXXX Data D15-D0 D15-D0
Writes register. Write enable must precede all programming modes. Disables all programming instructions.
Comments
Reads data stored in memory, at specified address.
D15-D0
Writes all registers.
X: Don't care table3. Instruction Set for the AK93C10A (Note) The WRAL instruction are used for factory function test only. User can't use the WRAL instruction. The AK93C85A perceives the start bit in the logic"01" and also "001". The AK93C95A/10A perceives the start bit in the logic"1" and also "01".
DAM02E-03 -4-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. AK93C85A: After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). AK93C95A/10A: The self-timed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the self-timed programming cycle is initiated. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
CS SK DI DO
0 0 1 1 0 2 1 3 4 A9 5 A8 12 A1 13 A0 14 D15 15 D14 27 D2 28 D1 29 D0 tCS
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C85A output a logic "1" (Ready status), if previous instruction is WRITE.
WRITE (AK93C85A)
CS SK DI DO
0 0 1 1 0 2 1 3 4 A10 5 A9 13 A1 14 A0 15 D15 16 D14 28 D2 29 D1 30 D0
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C95A output a logic "1" (Ready status), if previous instruction is WRITE.
WRITE (AK93C95A)
CS SK DI DO
0 0 1 1 0 2 1 3 4 A11 5 A10 14 A1 15 A0 16 D15 17 D14 29 D2 30 D1 31 D0
Start Bit
Op code
Hi-Z
Busy Ready tE/W
AK93C10A output a logic "1" (Ready status), if previous instruction is WRITE.
WRITE (AK93C10A)
DAM02E-03 -52004/05
ASAHI KASEI
[AK93C85A/95A/10A]
READ
The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. AK93C85AWhen the highest address is reached ($3FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK93C95AWhen the highest address is reached ($7FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK93C10AWhen the highest address is reached ($FFF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely.
CS SK DI DO
0 0 1 1 1 2 0 3 4 A9 5 A8 12 A1 13 A0 14 15 29 30 44 45
Start bit
Op code
Hi-Z
AK93C85A output a logic "1" (Ready status), if previous instruction is WRITE.
0 D15 D14 D0 Dummy address[A9-A0] Bit
D15
D1
D0
address[A9-A0]+1
READ (AK93C85A)
CS SK DI DO
0 0 1 1 1 2 0 3 4 A10 5 A9 13 A1 14 A0 15 16 30 31 45 46
Start bit
Op code
Hi-Z
AK93C95A output a logic "1" (Ready status), if previous instruction is WRITE.
0 D15 D14 D0 Dummy address[A10-A0] Bit
D15
D1
D0
address[A10-A0]+1
READ (AK93C95A)
CS SK DI DO
0 0 1 1 1 2 0 3 4 A11 5 A10 14 A1 15 A0 16 17 31 32 46 47
Start bit
Op code
Hi-Z
AK93C10A output a logic "1" (Ready status), if previous instruction is WRITE.
0 D15 D14 D0 Dummy address[A11-A0] Bit
D15
D1
D0
address[A11-A0]+1
READ (AK93C10A)
DAM02E-03 -62004/05
ASAHI KASEI
[AK93C85A/95A/10A]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions.
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
12 X
13 X
Start bit
AK93C85A output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C85A)
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
12 X
13 X
14 X
Start bit
AK93C95A output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C95A)
CS SK DI DO
0 0 1 1 0 2 0 EWEN=11 EWDS=00
Hi-Z
3
4
5 X
6 X
7 X
8 X
9
10 X
11 X
12 X
13 X
14 X
15 X
Start bit
AK93C10A output a logic "1" (Ready status), if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C10A)
DAM02E-03 -7-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
Absolute Maximum Ratings
Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol VCC VIO Tst Min -0.6 -0.6 -65 Max +7.0 VCC+0.6 +150 Unit V V C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta Min 1.8 -40 Max 5.5 +85 Unit V C
DAM02E-03 -8-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS ( 1.8V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Parameter Current Dissipation (WRITE) Current Dissipation
(READ, EWEN, EWDS)
Symbol ICC1 ICC2 ICC3 ICC4 ICCSB VIH VIL VOH1 VOH2
Condition VCC=5.5V, tSKP=1.0s, *1 VCC=1.8V, tSKP=4.0s, *1 VCC=5.5V, tSKP=1.0s, *1 VCC=1.8V, tSKP=4.0s, *1 VCC=5.5V *2
Min.
Max. 5.5 3.0 0.4 0.1 0.8
Unit mA mA mA mA A V V V V
Current Dissipation (Standby) Input High Voltage Input Low Voltage Output High Voltage
0.8 x VCC -0.1 2.5V VCC 5.5V IOH=-0.1mA 1.8V VCC < 2.5V IOH=-0.1mA 2.5V VCC 5.5V IOL=1.0mA 1.8V VCC < 2.5V IOL=0.1mA VCC=5.5V, VIN=5.5V VCC=5.5V, VOUT=5.5V, CS=GND 0.8 x VCC 0.8 x VCC
VCC + 0.5 0.2 x VCC
Output Low Voltage
VOL1 VOL2
0.4 0.4 1.0 1.0
V V A A
Input Leakage Output Leakage
ILI ILO
*1 : VIN=VIH/VIL, DO=Open *2 : VIN=VCC/GND, CS=GND, DO=Open
DAM02E-03 -9-
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
(2) A.C. ELECTRICAL CHARACTERISTICS ( 1.8V VCC 5.5V, -40C Ta 85C, unless otherwise specified ) Parameter SK Cycle Time Symbol tSKP1 tSKP2 tSKP3 SK Pulse Width tSKW1 tSKW2 tSKW3 CS Setup Time CS Hold Time Data Setup Time Data Hold Time Output delay *3 tCSS tCSH tDIS tDIH tPD1 tPD2 tPD3 Selftimed Programming Time Min CS Low Time CS to Status Valid1 CS to Status Valid2 CS to Output High-Z tE/W1 tE/W2 tCS tSV tSVV tOZ1 tOZ2 *3 : CL=100pF CL=100pF CL=100pF 2.0V VCC 5.5V 1.8V VCC < 2.0V 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V 4.5V VCC 5.5V 1.8V VCC < 4.5V 250 500 1000 100 250 Condition 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V 4.5V VCC 5.5V 2.0V VCC < 4.5V 1.8V VCC < 2.0V Min. 1.0 2.0 4.0 500 1.0 2.0 100 0 200 200 500 1.0 2.0 8 10 Max. Unit s s s ns s s ns ns ns ns ns s s ms ms ns ns ns ns ns
DAM02E-03 - 10 -
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
Synchronous Data timing
tCS
CS
tCSS tSKW tSKW tSKP
SK
tDIS tDIH
DI
tSV
0
1
DO
Hi-Z
AK93C85A/95A/10A output a logical "1" (Ready status), if previous instruction is WRITE.
The Start of Instruction
CS
tCSH
SK DI
tPD tPD tPD tOZ
DO
D3
D2
D1
D0
Hi-Z
The End of Instruction
DAM02E-03 - 11 -
2004/05
ASAHI KASEI
[AK93C85A/95A/10A]
tCS
CS
tCSH
SK
tDIS tDIH
DI DO
D1
D0
tSV Hi-Z Busy Ready
tE/W
Busy/Ready Signal Output (AK93C85A)
CS SK
tDIS tDIH
DI DO
D1
D0
tSVV Hi-Z Busy Ready tOZ
tE/W
Busy/Ready Signal Output (AK93C95A/10A)
DAM02E-03 - 12 -
2004/05
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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